1. Field of the Invention
The present invention relates to an interconnecting substrate used for carrying a semiconductor chip and a semiconductor device in which this interconnecting substrate is used.
2. Description of the Related Art
In recent years, as a result of an increase in the number of terminals and a narrower pitch due to the high performance design, multifunctional design and high density design of semiconductor devices, interconnecting substrates for packaging on which semiconductor devices are to be mounted have been required to provide high density and fine pitch design more than before.
A build-up printed substrate, which is a type of a multilayer interconnecting substrate, has hitherto been-mentioned as an interconnecting substrate for packaging which is widely used. In this builtup printed substrate, resin layers are formed on both surfaces of a glass epoxy printed substrate as a base core substrate, on which interconnections are formed, and in these resin layers, via holes are formed by the photolithography process and the laser process and then interconnection layers and via conductors are formed by the plating process and the photolithography process. A multilayer interconnection structure can be formed by repeating the resin layer forming step and the interconnection and via conductor forming step as required.
However, this builtup printed substrate has the problem that because of the use of a glass epoxy printed substrate of low heat resistance as the base core substrate, deformation, such as shrinkage, warpage and waviness, is apt to occur due to the heating during the formation of a multilayer structure and the carrying of a semiconductor chip.
On the other hand, the JP2000-3980A (Patent Document 1) discloses an interconnecting substrate for packaging in which a builtup laminated structure is formed on a base substrate made of a metal sheet.
FIGS. 9(a) to 9(d) each show a manufacturing process diagram of this interconnecting substrate for packaging. First, as shown in FIG. 9(a), insulating layer 502 is formed on metal sheet 501 and via hole 503 is formed in this insulating layer 502. Next, as shown in FIG. 9(b), interconnection pattern 504 is formed on insulating layer 502 in which via hole 503 is formed. Next, as shown in FIG. 9(c), insulating layer 506 is formed on interconnection pattern 504, and flip chip pad portion 505 which reaches interconnection pattern 504 is formed in this insulating layer 506. Lastly, as shown in FIG. 9(d), metal sheet 501 is etched from the bottom surface side and substrate-reinforcing body 507 and external electrode terminals 508 are formed.
However, because in this interconnecting substrate for packaging, external electrode terminals 508 are formed by the etching of metal sheet 501, it is difficult to narrow the pitch between external electrode terminals 508 due to limits to the control of the quantity of side etching during etching. Furthermore, when this interconnecting substrate for packaging is mounted on an external board and a device, structurally, stresses are concentrated on the interface between external electrode terminal 508 and insulating layer 502, thereby posing the problem that open faults tend to occur and hence sufficient reliability cannot be obtained.
An interconnecting substrate for packaging capable of solving the above-described problems in conventional techniques is disclosed in the JP2002-198462A (Patent Document 2).
This basic structure and its manufacturing method will be described by using FIGS. 10(a) and 10(b). First, electrode 602 is formed on support board 601 made of a metal sheet etc., and insulating layer 603 is formed so as to cover this electrode. Next, via hole 604 which reaches electrode 602 is formed in this insulating layer 603 and interconnection 605 is formed so as to bury this via hole. This interconnection 605 is connected to electrode 602 by a conductor buried in the via hole (FIG. 10 (a)). A multilayer interconnection structure can be formed by repeating the steps for forming an insulating layer, a via hole and an interconnection as required. Next, as shown in FIG. 10(b), electrode 602 is exposed by selectively removing part of support board 601 by etching and support body 606 is formed. Interconnecting substrate 607 can be formed in this manner. Although a case where a pad-like electrode pattern is formed has been described here, it is also possible to form a linear interconnection pattern in a similar way.
The thermal deformation of the interconnecting substrate can be suppressed by using a heat-resistant material such as metal in support body 606, and a interconnecting substrate excellent in strength can be obtained by using a resin material having a desired mechanical strength for the insulating layer. Furthermore, because the bottom surface is exposed, with the circumference of the conductor layer, such as the electrode and the interconnection, buried in the insulating layer, stresses applied to the conductor layer is suppressed during mounting and hence mounting reliability can be increased.
Also, insulating layer materials suitable for the above-described interconnecting substrate are disclosed in JP2004-179647A (Patent Document 3). For the purpose of providing an interconnecting substrate and a semiconductor package which possess high reliability, where the formation of cracks due to repeatedly applied thermal stresses are suppressed, this document discloses an insulating layer which has a film thickness of 3 to 100 μm, a fracture strength of not less than 80 MPa at 23° C. and values of the ratio (a/b) of not more than 4.5 when the fracture strength at −65° C. is denoted by “a” and the fracture strength at 150° C. is denoted by “b”. In addition to this, it is specified that the modulus of elasticity at 150° C. is preferably not less than 2.3 GPa. Also, this document discloses that when the modulus of elasticity at −65° C. is denoted by “c” and the modulus of elasticity at 150° C. is denoted by “d”, values of the ratio (c/d) are specified at not more than 4.7. Furthermore, this document discloses that values of the ratio (a/b) are specified at not more than 2.5, or values of the ratio (a/b) are specified at larger than 2.5 but not more than 4.5 and absolute values of a difference between the ratio (a/b) and the ratio (c/d) are specified at not more than 0.8.
However, an interconnecting substrate having a structure as described in Patent Document 2 had the problem that a warpage occurs after manufacture although it is excellent in heat resistance and mechanical strength according to the characteristics of an insulating material. For example, in a case where, from the standpoint of productivity, a block substrate in which region units that correspond to target interconnecting substrates are arrayed as blocks in one substrate is formed, a warpage occurs in such a manner that the whole of this block substrate is bent. This block substrate is transferred after its manufacture and is cut and divided into individual target packages that correspond to the target interconnecting substrates after mounting semiconductor chips on the block substrate. On that occasion, the warpage of the block substrate lowers transfer efficiency, and makes it difficult to perform precise mounting of semiconductor chips, thereby causing a decrease in throughput, yield and connection reliability.